In modem digital radio design, the RF frequency synthesizer is a key block used for both up-conversion and down-conversion of radio signals. Traditionally, it has been based on a charge-pump PLL which is not easily amenable to scaled CMOS integration and suffers from high level of reference spurs generated by the correlative phase detection method. Use of a digitally-controlled oscillator (DCO) that deliberately avoids any analog tuning controls has been proposed and demonstrated for RF wireless applications. This allows for the loop control circuitry to be implemented in a fully digital manner as a digital-synchronous phase-domain all-digital PLL (ADPLL), which has been implemented commercially in single-chip Bluetooth and GSM radios.
A high level block diagram illustrating a prior art all digital phase-domain PLL (ADPLL) is shown in FIG. 1. The ADPLL, generally referenced 31, comprises a reference phase accumulator 32, time to digital converter (TDC) system 34, phase detector 36, loop filter 38, DCO gain normalizer 40 and DCO 42.
Since the conventional phase/frequency detector and charge pump are replaced in these designs by a time-to-digital converter (TDC), the phase-domain operation does not fundamentally generate any reference spurs thus allowing for the digital loop filter to be set at an optimal performance point between the reference phase noise and oscillator phase noise.
An important issue in frequency synthesis for today's wireless applications is the acquisition or settling time to a new channel frequency from the trigger event to the instance when the wireless terminal is ready to transmit or receive with the specified low level of frequency error, phase noise and spurious tones. Loop bandwidth in traditional PLL circuits is fixed to a narrow value during most part of the settling interval in order to guarantee proper quality of the synthesized clock during the normal operation. Unfortunately, it also severely slows down the loop dynamics. This difficulty in performing the PLL bandwidth switchover or gear shifting limits the PLL settling time to typically no less than a hundred μs, as is the case in many currently available commercial handset RF transceivers. One prior art base station PLL exhibits a 10 μs settling time but this was achieved by means of large area, high complexity and large current consumption.
The gain of PLL control loops often requires special settings for different modes of operation. Gear shifting changes the gain of the control loop to suit the various operating modes. For example, it is desirable to have high loop bandwidth while initially locking in acquisition mode in order that the PLL settle quickly. In tracking mode, however, it is desirable to have a low loop bandwidth to increase the performance of the PLL. A change in loop gain, however, typically causes an undesirable frequency step in the oscillator output.
Typically, it is difficult to perform PLL gear shifting in analog circuits because of the imperfect matching and voltage or charge losses during switching which results in phase hits whenever a sudden perturbation (i.e. gear-shift) is introduced. One prior art attempt to provide bandwidth switching performs a time-continuous adaptive gear-shifting for clock recovery applications. The loop gain is gradually reduced based on the filtered phase variations. As the loop settles, the phase detector output produces less and less variations at its output causing less charge to be stored on a capacitor. This is used, in turn, to gradually reduce bias in the charge pump, thus reducing the overall loop gain. Since the charge pump current is dynamically controlled, however, this creates an additional source of phase noise at the VCO input.
In another prior art attempt the variable loop bandwidth is switched by changing the charge pump current together with PLL loop filter parameters. Due to the switching issues, however, the achieved speedup is limited.
There is thus a need for a gear shift mechanism that can be used within an ADPLL to maximally speed up by at least an order of magnitude the acquisition of new channel frequencies. The gear shift mechanism should allow the ADPLL to provide adequate RF performance of a targeted wireless standard. Further, the mechanism should permit the PLL to start with an ultra-wide acquisition bandwidth that is progressively narrowed down. Moreover, it is desirable that the bandwidth switching carried out by the gear shifting mechanism be hitless through the entire settling and operational intervals.